register level
英 [ˈredʒɪstə(r) ˈlevl]
美 [ˈredʒɪstər ˈlevl]
网络 注册级; 寄存器级
双语例句
- Verification is the bottleneck of more and more complex integrated circuit designs, and doing verification directly on register transfer level ( RTL) is a promising solution.
验证是当前越来越复杂的集成电路设计中的瓶颈，在寄存器传输级（RTL）直接做验证是目前比较有效的一种途径。 - If I pass the Level I exam in December, can I register for the Level II exam held the following June?
如果我十二月通过了一级考试，在次年的六月我能报考二级吗？ - Register transfer level simulator
寄存偏送级模拟程序多路转换器模拟程序 - We base on it to establish abstract model between the sequential executable codes and the register transfer level ( RTL) description.
我们依该方法在循序可执行程式码和暂存器传输层级间建立抽象模型。 - This paper analyzes the cause of its formation from register level, make contrastive analysis from lexical level and summarize its stylistic feature and stylistic effects.
文章从语域角度分析网络聊天室语言的成因，并从词汇角度对中英网络聊天语言进行对比分析，总结其文体特征及文体效果。 - The main task is translating the behavioral description of a digital system into the design of RTL ( Register Transfer Level).
高层次综合也叫行为级综合，其基本任务是完成数字系统行为描述到寄存器传输级（RTL）描述的转换。 - Mappings of Gate Level Faults to Register Transfer Level Faults
门级故障到寄存器传输级故障的映射 - In particular, the increased delay may cause delay faults. paper [ 1] proposed two power-constrained non-scan BIST methods for register transfer level ( RTL) data paths.
针对寄存器传输级（RTL）数据通路，文献[1]提出了两种功耗限制下非扫描内建自测试（BIST）方法。 - Register Transfer Level Coverage-Driven Verification of External Memory Interface
RTL级基于覆盖率驱动EMI的验证 - A register translation level ( RTL) module design method of Data-RAM for double precision float-point digital signal processor is proposed.
提出了一种双精度浮点数字信号处理器Data-RAM的RTL模型设计方法。 - A Test Case Generation Method at Register Transfer Level
寄存器传输级测试用例生成算法 - The above work is intended to set up an automatic logic synthesis system to translate a register transfer level language descriptions into hardware logic diagrams.
上述工作是为了建立一个将寄存器传输级语言描述翻译成硬件逻辑图的自动逻辑综合系统。 - Test Generation Based on Hiberarchy Model at Register Transfer Level
基于寄存器传输级层次模型的测试生成研究 - RTL ( register transfer level) functional verification system for package assembly function in IPOA application is illustrated in this paper.
介绍一种对IPOA应用中的组包功能进行RTL功能验证的系统。 - The Register Transfer Level ( RTL) behavioral descriptions are widely used in IC designs.
寄存器传输级（RTL）描述是目前应用最广泛的电路设计描述形式。 - The growing complexity of modern ICs is driving the trend of automatic test pattern generation ( ATPG) towards testing at high level, particularly at register transfer level ( RTL).
寄存器传输级（RTL）测试产生及时延测试是当今集成电路（IC）测试技术中亟待解决的问题和研究的热点。 - As the behavior of digital system can be fully described by the register transfer level ( RTL) behavior descriptor, so RTL synthesis has become the mainstream design method in EDA domain.
寄存器传输级（RTL）综合实现从RTL行为描述到门级结构描述的转换，是目前EDA设计行业的主流设计方法。 - A domain fault model of Verilog RTL ( Register Transfer Level) code and the corresponding domain-testing strategies are proposed.
本文提出了一种VerilogRTL（Registertransferlevel）代码域故障模型和相应的测试点生成策略。 - Grade. We implement and verify the DES circuit on behavior level and Register Transfer Level ( RTL).
本文分别从行为级和RTL级实现并且验证了DES电路。 - High Level Synthesis Method for Clustered Register Transfer Level Architecture
面向分模块寄存器传输级结构的高层次综合方法 - Sequential Depth of Integrate Circuits Based on Register Transfer Level
RTL集成电路的时序深度 - The influence of architectures on synthesis methods is discussed, and a clustered register transfer level architecture as object architecture is presented.
文章讨论了寄存器传输级结构对综合方法的影响，并提出使用分模块的寄存器传输级结构作为高层次综合的目标结构。 - In IC design, it is a common method to set up behavior models for target systems by RTL ( Register Transfer Level) Verilog codes. People can find the potential logic bugs and primarily evaluate the performance of target systems by deploying software simulation for RTL codes.
在IC设计中，使用Verilog编写寄存器级描述（RTL）对目标系统建立行为级模型后，对RTL进行大量的软件仿真不仅可以及早发现潜在的逻辑错误，而且能够对目标系统的性能进行初步评估。 - Completed the circuits design using Register Transfer Level method.
采用面向可综合的寄存器传输级设计方法完成电路设计； - Micro-architectures are based on the same template, the register transfer level description of ASIP can be automatically generated.
微结构设计遵循统一模板，其寄存器传输级描述可自动生成。 - Hardware Description Language is used to designs of Register Transfer Level, but Hardware Verification Language needs more abstract characteristic, which causes mutually exclusive direction of development of them and makes the process of design and verification complex.
硬件描述语言用于寄存器传输级的设计，而验证语言需要更加抽象的性能，这样就造成了硬件描述语言与硬件验证与语言的分向发展，从而使整个设计和验证的过程变得复杂。 - The design are being changed from the original register transfer level ( RTL) to the System-level ( ESL), and the resulting system-level design language ( SDL) is also becoming available.
集成电路设计也从原来的寄存器传输级（RTL）转向系统级（ESL），由此系统级设计语言也适时而生。 - It also shows the sub-module for each module schematic and RTL ( Register Transfer Level) level integrated structure in the thesis.
论文还对每个模块给出了子模块原理图和RTL（Registertransferlevel）级综合结构图。 - Finally, the architecture is described by Verilog HDL in register transfer level ( RTL). The synthesis, simulation and on-line debugging of this design are implemented with the assistance of EDA tools. And the result of simulation and synthesis is given out.
最后，采用Verilog硬件描述语言对整个结构进行寄存器传输级描述，用EDA工具完成了整个设计的仿真和综合，给出了仿真和综合的结果。 - Register transfer level code verification is the most important factor in the design, therefore, two ways are analyzed in this thesis: logic function simulation and prototype verification.
寄存器传输级代码的验证是保证芯片功能正确的最关键因素，为此，本文讨论了逻辑功能仿真验证和原型验证这两种方法。